While some recent NDA proposals acknowledge the need for NDA–CPU coherence [4, 25, 26, 126], these works largely sidestep the issue by assuming that the NDA and CPU share only a limited amount of data.
These costs are often exacerbated by the fact that much of the data brought into the caches is not reused by the CPU [52, 53, 55, 56], providing little benefit in return for the high latency and energy cost.
Without approximating some calculations, the number of interatomic forces computed on each time step scales quadratically with the number of atoms, meaning there is an enormous increase in time-to-solution with increasing system size.
Despite the significant benefits of accelerators, system challenges remain a main stumbling block to the mainstream adoption of specialized accelerators.
However, if the PIM logic needs to communicate with existing CPU-side address translation mechanisms, the benefits of PIM could easily be nullified, as each address translation would need to perform a long latency request across the memory channel.
While these two challenges represent some of the largest obstacles to widespread adoption for PIM, a number of other important challenges remain, which we discuss briefly in Section 6.
The data movement bottleneck incurs a heavy penalty in terms of both performance and energy consumption [13–20].
However, exploiting Complex Addressing to improve performance is challenging for a number of reasons.
Jointly considering these factors is challenging since they are impacted by the complex interaction between many features of the application, the input data, and the underlying architecture.
As a consequence, it is increasingly difficult to predict, explain, let alone optimize the performance of software running on such microarchitectures.